ICS8732-01 Datasheet, PDF (10/17 Pages) Integrated Device Technology – Maximum output frequency

ICS8732-01
LOW VOLTAGE, LOW SKEW
3.3V LVPECL CLOCK GENERATOR
LAYOUT GUIDELINE
Figure 5 shows a schematic example of the ICS8732-01. In this
example, the CLK0/nCLK0 input is selected. The decoupling ca-
pacitors should be physically located near the power pin. For
ICS8732-01, the unused outputs can be left floating.
VCC R14
1K
VCC
R7 10
VCC
C16
10uF
Zo = 50
VCCA
C11
0.1uF
DIV_SELA1
DIV_SELA0
LVPECL
Zo = 50
R1 R2
50 50
R3
50
DIV_SELB1
DIV_SELB0
R13
1K
14
15
16
DIV_SELA1
DIV_SELA0
17 ^VCC
18
19
20
21
VEE
CLK1
nCLK0
CLK0
22
23
24
25
26
CLK_SEL
VCCA
nc
DIV_SELB1
DIV_SELB0
VCC
VCC
U1
ICS8732-01
VEE
FBDIV_SEL2
52
51
50
FBDIV_SEL1 ₄₉
FBDIV_SEL0
nF B_I N
FB_IN
VCC
48
47
46
45
VEE
nQF B0
QF B0
nQF B1
QF B1
44
43
42
41
40
VCCO
Zo = 50
Zo = 50
F BD I V_SEL2
F BD I V_SEL1
F BD I V_SEL0
+
-
R4
R5
50
50
R6
50
R10
50
R11
50
R12
50
Logic Input Pin Examples
Set Logic
VCC
Input to
'1'
RU1
1K
To Logic
Input
pins
RD1
SP
Set Logic
VCC
Input to
'0'
RU2
SP
To Logic
Input
pins
RD2
1K
Zo = 50
VCC=3.3V
SP = Spare (i.e. not intstalled)
(U1-1)
(U1-8)
VCC
(U1-16) (U1-26)
(U1-32)
(U1-39)
(U1-40)
Zo = 50
(U1-46)
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
Bypass capacitors located near the power pins
+
-
R8
R7
50
50
R9
50
FIGURE 5. ICS8732-01 LVPECL BUFFER SCHEMATIC EXAMPLE
8732AY-01
www.idt.com
10
REV. E MAY 2, 2013