ICS8536I-33 Datasheet, PDF (2/19 Pages) Integrated Device Technology – LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOSTO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER

ICS8536I-33
LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Synchronizing clock enable. When HIGH, clock outputs follows clock
1
CLK_EN
Input Pullup input. When LOW, Q outputs are forced low, nQ0 output is forced high.
LVCMOS / LVTTL interface levels.
2,
3
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
4
V_CC
Power
Positive supply pins.
5
CLK
Input Pulldown Single-ended clock input. LVCMOS / LVTTL interface levels.
6
7, 15,
20
CLK_SEL
V_EE
Input
Power
Pullup
Clock select input. When HIGH, selects XTAL inputs.
When LOW, selects CLK input. LVCMOS / LVTTL interface levels.
Negative supply pin.
8, 9
Q0, nQ0 Output
Differential clock outputs. LVPECL interface levels.
10
11, 12
V_{CCO_LVPECL}
Q1, nQ1
Power
Output
Output power supply mode for LVPECL clock outputs.
Differential clock outputs. LVPECL interface levels.
13, 14
nQ2, Q2 Output
Differential clock outputs. LVPECL interface levels.
16, 18, 19 Q3, Q4, Q5 Output
Single ended clock outputs. LVCMOS / LVTTL interface levels.
17
V_{CCO_LVCMOS}
Power
Output power supply mode for LVCMOS / LVTTL clock outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C_PD
Parameter
Input Capacitance
Power Dissipation
Capacitance (per output)
Q3:Q5
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance
Q3:Q5
Q3:Q5
Test Conditions
V_CC, V_{CCO_LVCMOS} = 3.465V
V_CC, V_{CCO_LVCMOS} = 2.625V
V_CC, V_{CCO_LVCMOS} = 3.465V
V_CC, V_{CCO_LVCMOS} = 2.625V
Minimum
Typical
4
8
5
51
51
15
20
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
Ω
IDT^™ / ICS^™ 3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER
2
ICS8536CGI-33 REV. B OCTOBER 27, 2008