ICS850S1201I Datasheet, PDF (2/12 Pages) Integrated Device Technology – 12:1 SINGLE-ENDED MULTIPLEXER

ICS850S1201I
12:1, SINGLE-ENDED MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6,
7.
8,
9
10
11
12
13
14
15
16
17
18
19
20
Name
CLK8
CLK9
CLK10
CLK11
V_DD
CLK_SEL0,
CLK_SEL1,
CLK_SEL2,
CLK_SEL3
OE
Q
GND
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Type
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Pulldown
Power
Description
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Power supply pin.
Input
Pulldown Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.
Input
Output
Power
Input
Input
Input
Input
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Output enable pin for Q output. LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
Parameter
Input Capacitance
C_PD
Power Dissipation Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance
Test Conditions
V_DD = 3.465V
V_DD = 2.625V
V_DD = 3.3V±5%
V_DD = 2.5V±5%
Minimum
Typical
2
10
8
51
51
20
25
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
Ω
IDT™ / ICS™ 12:1, SINGLE-ENDED MULTIPLEXER
2
ICS850S1201BGI REV. A AUGUST 15, 2008