ICS844002I-01 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 7
2, 20
3, 4
5
6
8
9,
11
10
12,
13
14
Name
nc
V_DDO
Q0, Q0
MR
PLL_SEL
V_DDA
FSEL0,
F_SEL1
V_DD
XTAL_OUT_,
XTAL_IN
REF_CLK
Type
Unused
Power
Output
Input Pulldown
Input Pulldown
Power
Description
No connect.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs Qx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Power
Input
Input
Pulldown
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Non-inverting differential clock input.
15
16
17
18, 19
XTAL_SEL
nc
GND
Q1, Q1
Input
Unused
Power
Output
Pulldown
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
No connect.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
2
ICS844002AGI-01 REV. C SEPTEMBER 28, 2007