ICS844001-21 Datasheet, PDF (2/17 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_{DDO_CMOS}
Power
Output supply pin for LVCMOS output.
2, 3
N0, N1
Input Pullup _{Output divider select pins. Default ÷4.}
4
N2
Input Pulldown ^{LVCMOS/LVTTL interface levels.}
5
V_{DDO_LVDS}
Power
6, 7
Q, nQ
Ouput
Output supply pin for LVDS outputs.
Differential output pair. LVDS interface levels.
8, 23
GND
Power
Power supply ground.
9
V_DDA
Power
10
V_DD
Power
11
12
XTAL_OUT1,
XTAL_IN1
Input
13
14
XTAL_OUT0,
XTAL_IN0
Input
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
15
REF_CLK Input Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
16, 17 SEL0, SEL1 Input Pulldown MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
18
MR
Input
Pulldown
reset causing the true output Q to go low and the inverted output nQ to
go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
19, 20
21
22
M0, M1
M2
REF_OE
Input
Input
Input
Pulldown _{Feedback divider select pins. Default ÷32.}
Pullup ^{LVCMOS/LVTTL interface levels.}
Pulldown
Reference clock output enable. Default Low.
LVCMOS/LVTTL interface levels.
24
REF_OUT Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
R_PULLUP
R_out
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance REF_OUT
Test Conditions
Minimum
Typical
4
51
51
7
Maximum
Units
pF
kΩ
kΩ
Ω
IDT^™ / ICS^™ INSERT PRODUCT NAME
2
ICS844001AG-21 REV. A SEPTEMBER 14, 2007