ICS571 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Low Phase Noise Zero Delay Buffer

ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
Pin Assignment
ZDB AND MULTIPLIER/DIVIDER
Feedback Configuration Table and Frequency Ranges (at 3.3 V)
Feedback From
CLK
CLK/2
CLK
Input clock frequency
2x Input clock frequency
CLK/2
Input clock frequency/2
Input clock frequency
Input Range
20 to 160 MHz
10 to 80 MHz
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
VDD
GND
CLK/2
GND
VDD
CLK
FBIN
Pin
Type
CI
P
P
O
P
P
O
CI
Pin Description
Reference clock input.
Connect to +3.3 V or +5 V. Must be same as other VDD.
Connect to ground.
Clock output per table above. Low skew divide by two of pin 7 clock.
Connect to ground.
Connect to +3.3 V or +5 V. Must be same as other VDD.
Clock output per table above.
Feedback clock input. Connect to CLK or CLK/2 per table above.
Key: CI = clock input; I = input; O = output; P = power supply connection.
IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER
2
ICS571
REV H 051310