ICS551MILF Datasheet, PDF (2/9 Pages) Integrated Device Technology – 1 TO 4 CLOCK BUFFER

ICS551
1 TO 4 CLOCK BUFFER
Pin Assignment
ICLK 1
Q1 2
Q2 3
Q3 4
8 OE
7 VDD
6 GND
5 Q4
8 Pin (150 mil) SOIC
FAN OUT BUFFER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Pin Description
Input Clock input. Internal pull-up resistor.
Output Clock output 1.
Output Clock output 2.
Output Clock output 3.
Output Clock output 4.
Power Connect to ground.
Power Connect to 3.3 V or 5.0 V.
Input Output Enable. Tri-states outputs when low. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible.
A 33Ω series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
IDT™ 1 TO 4 CLOCK BUFFER
2
ICS551
REV P 051310