ICS551MILF Datasheet, PDF (1/9 Pages) Integrated Device Technology – 1 TO 4 CLOCK BUFFER

1 TO 4 CLOCK BUFFER
DATASHEET
ICS551
Description
The ICS551 is a low cost, high-speed single input to
four output clock buffer. Part of IDT’s ClockBlocks^TM
family, this is our lowest cost, small clock buffer.
See the ICS552-02B for monolithic dual version of the
ICS551 in a 20 pin QSOP.
IDT makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact IDT for all of your clocking
needs.
Features
• Low skew (250 ps) outputs
• Pb-free packaging
• Low cost clock buffer
• Packaged in 8-pin SOIC
• Input/Output clock frequency up to 160 MHz
• Non-inverting output clock
• Ideal for networking clocks
• Operating Voltages of 3.3 and 5.0 V
• Output Enable mode tri-states outputs
• Advanced, low power CMOS process
• Commercial and industrial temperature versions
Block Diagram
ICLK
Q1
Q2
Q3
Q4
Output Enable
IDT™ 1 TO 4 CLOCK BUFFER
1
ICS551
REV P 051310