ICS524 Datasheet, PDF (2/7 Pages) Integrated Device Technology – LOW SKEW 1 TO 4 CLOCK BUFFER

ICS524
LOW SKEW 1 TO 4 CLOCK BUFFER
Pin Assignment
ICLK
1
Q0
2
Q1
3
NC
4
8 GND
7
Q3
6
Q2
5 VDD
8-pin SOIC
FAN OUT BUFFER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q0
Q1
NC
VDD
Q2
Q3
GND
Pin
Type
Input
Output
Output
-
Power
Output
Output
Power
Pin Description
Clock input, 5V tolerant input.
Clock output 0.
Clock output 1.
Do not connect this pin to anything.
Connect to +2.5 V, +3.3 V or +5.0 V.
Clock Output 2.
Clock Output 3.
Connect to ground.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF
should be connected between VDD on pin 5 and GND on pin 8, as close to the device as possible. A 33 Ω series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS524 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they
do not, the output skew will be degraded. For example, using a 30Ω series termination on one output (with 33Ω on
the others) will cause at least 15 ps of skew.
IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER
2
ICS524
REV A 101705