9ZX21201 Datasheet, PDF (2/16 Pages) Integrated Device Technology – 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI

9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 1
48 GND
GNDA 2
47 DIF_7#
IREF 3
46 DIF_7
100M_133M# 4
45 vOE7#
HIBW_BYPM_LOBW# 5
44 vOE6#
CKPWRGD_PD# 6
43 DIF_6#
GND 7
42 DIF_6
VDDR 8
DIF_IN 9
9ZX21201
41 GND
40 VDD
DIF_IN# 10
39 DIF_5#
SMB_A0_tri 11
38 DIF_5
SMBDAT 12
37 vOE5#
SMBCLK 13
36 vOE4#
SMB_A1_tri 14
35 DIF_4#
DFB_OUT# 15
34 DIF_4
DFB_OUT 16
33 GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Notes: Pins with ^ prefix have internal ~100K pullup
Pins with v prefix have internal ~100K pulldown.
Tri-level Input Thresholds
Level
Voltage
Low
<0.8V
Mid
1.2<Vin<1.8V
High
Vin > 2.2V
Functionality at Power Up (PLL Mode)
100M_133M#
DIF_IN
(MHz)
1
100.00
0
133.33
DIF
DIF_IN
DIF_IN
PLL Operating Mode Readback Table
HiBW_BypM_LoBW# Byte0, bit 7
Low (Low BW)
0
Mid (Bypass)
0
High (High BW)
1
Byte 0, bit 6
0
1
1
PLL Operating Mode
HiBW_BypM_LoBW#
Low
Mid
MODE
PLL Lo BW
Bypass
High
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
IDT^® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
MLF Power Connections
Pin Number
VDD
1
VDD
GND
2
8
7
23,33,41,48,
25,40,56 24,32,49,57
58
Description
Analog PLL
Analog Input
DIF clocks
9ZX21201 SMBus Addressing
Pin
SMBus Address
SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0)
0
0
D8
0
M
DA
0
1
DE
M
0
C2
M
M
C4
M
1
C6
1
0
CA
1
M
CC
1
1
CE
1682B- 12/08/11
2