9DBU0941_17 Datasheet, PDF (2/17 Pages) Integrated Device Technology – 9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms

9DBU0941 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
36 DIF5#
vOE8# 2
35 DIF5
DIF8 3
34 vOE4#
DIF8# 4
33 DIF4#
VDDR1.5 5
CLK_IN 6
9DBU0941
32 DIF4
31 VDDIO
CLK_IN# 7
GNDR 8
epad is GND
30 VDDO1.5
29 GND
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.5 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
SMBus Address Selection Table
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low
Low
Low
Low
Running
Running
Low
Low
Power Connections
Pin Number
VDD
5
VDDIO
GND
8
Description
Input receiver
analog
12
20,30,31,38
9
13,21,31,39,47 22,29,40
Digital power
DIF outputs
Note: EPAD on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
9-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
2
MARCH 9, 2017