89HPES34H16G2 Datasheet, PDF (2/54 Pages) Integrated Device Technology – Low latency cut-through architecture

IDT 89HPES34H16G2 Data Sheet
– All ports support hot-plug using low-cost external I²C I/O
expanders
– Configurable presence detect supports card and cable appli-
cations
– GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system
support
– Hot-swap capable I/O
 _{Power Management}
– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)
• Supports L0, L0s, L1, L2/L3 Ready and L3 link states
• Configurable L0s and L1 entry timers allow performance/
power-savings tuning
– Supports PCI Express Power Budgeting Capability
– SerDes power savings
• Supports low swing / half-swing SerDes operation
• SerDes optionally turned-off in D3hot
• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
 _{32 General Purpose I/O}
 _{Reliability, Availability and Serviceability (RAS)}
– ECRC support
– AER on all ports
– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Autonomous link reliability (preserves system operation in the
presence of faulty links)
– Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
 _{Test and Debug}
– On-chip link activity and status outputs available for Port 0
(upstream port)
– Per port link activity and status outputs available using
external I²C I/O expander for all other ports
– SerDes test modes
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
 _{Power Supplies}
– Requires only two power supply voltages (1.0 V and 2.5 V)
Note that a 3.3V is preferred for V_DDI/O
– No power sequencing requirements
 _{Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with}
1mm ball spacing
– Compatible with IDT 89HPES34H16 PCIe Gen1 switch
Note: For pin compatibility issues, contact the IDT help desk
at [e-mail].
Product Description
Utilizing standard PCI Express interconnect, the PES34H16G2
provides the most efficient I/O connectivity for applications requiring
high throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 34 GBps (272 Gbps) of aggregated,
full-duplex switching capacity through 34 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 GT/s of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES34H16G2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers. The PES34H16G2 can operate either as a store
and forward switch or a cut-through switch. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to enable efficient switching and I/O connectivity.
The PES34H16G2 is a partitionable PCIe switch. This means that in
addition to operating as a standard PCI express switch, the
PES34H16G2 ports may be partitioned into groups that logically
operate as completely independent PCIe switches. Figure 2 illustrates a
three partition PES34H16G2 configuration.
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November 28, 2011