89HPES34H16G2 Datasheet, PDF (1/54 Pages) Integrated Device Technology – Low latency cut-through architecture

34-Lane 16-Port PCIe® Gen2
System Interconnect Switch
®
89HPES34H16G2
Data Sheet
Device Overview
The 89HPES34H16G2 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES34H16G2 is a 34-lane, 16-
port peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
fifteen downstream ports and supports switching between downstream
ports.
Features
 _{High Performance Non-Blocking Switch Architecture}
– 34-lane 16-port PCIe switch
• Three x8 switch ports each of which can bifurcate to two x4
ports (total of six x4 ports)
• Ten x1 switch ports
– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
– Delivers up to 34 GBps (272 Gbps) of switching capacity
– Supports 128 Bytes to 2 KB maximum payload size
– Low latency cut-through architecture
– Supports one virtual channel and eight traffic classes
 _{Standards and Compatibility}
– PCI Express Base Specification 2.0 compliant
– Implements the following optional PCI Express features
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Power Budgeting Enhanced Capability
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting ECN
• Multicast ECN
• VGA and ISA enable
• L0s and L1 ASPM
• ARI ECN
– Compatible with IDT 89HPES34H16 PCIe Gen1 switch
 _{Port Configurability}
– x8, x4, and x1 ports
• Ability to merge adjacent x4 ports to create a x8 port
– Automatic per port link width negotiation
(x8 → x4 → x2 → x1)
– Crosslink support
– Automatic lane reversal
– Autonomous and software managed link width and speed
control
– Per lane SerDes configuration
• De-emphasis
• Receive equalization
• Drive strength
 _{Switch Partitioning}
– IDT proprietary feature that creates logically independent
switches in the device
– Supports up to 16 fully independent switch partitions
– Configurable downstream port device numbering
– Supports dynamic reconfiguration of switch partitions
• Dynamic port reconfiguration (downstream or upstream)
• Dynamic migration of ports between partitions
• Movable upstream port within and between switch partitions
 _{Initialization / Configuration}
– Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
– Common switch configurations are supported with pin strap-
ping (no external components)
– Supports in-system Serial EEPROM initialization/program-
ming
 _{Quality of Service (QoS)}
– Port arbitration
• Round robin
– Request metering
• IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
– High performance switch core architecture
• Combined Input Output Queued (CIOQ) switch architecture
with large buffers
 _Multicast
– Compliant to the PCI-SIG multicast ECN
– Supports arbitrary multicasting of Posted transactions
– Supports 64 multicast groups
– Multicast overlay mechanism support
– ECRC regeneration support
 _Clocking
– Supports 100 MHz and 125 MHz reference clock frequencies
– Flexible clocking modes
• Common clock
• Non-common clock
 _{Hot-Plug and Hot Swap}
– Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
 2011 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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November 28, 2011