843751 Datasheet, PDF (2/17 Pages) Integrated Device Technology – FemtoClock™ SAS/SATA Clock Generator

843751 Data Sheet
FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1,
2
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3,
4
SSC_SEL0,
SSC_SEL1
Input
Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
5
V_CC
Power
6, 7
Q, nQ
Output
Power supply pin.
Differential clock outputs. LVPECL interface levels.
8
V_EE
Power
Negative supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Function Tables
Table 3. SSC_SEL[1:0] Function Table
Inputs
SSC_SEL1
SSC_SEL0
Mode
0 (default)
0 (default)
SSC Off
0
1
0.5% Down-spread
1
0
0.5% Up-spread
1
1
0.5% Center-spread
843751 REVISION B 08.21.15
2
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