843751 Datasheet, PDF (10/17 Pages) Integrated Device Technology – FemtoClock™ SAS/SATA Clock Generator

843751 Data Sheet
FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
3.3V
R3
R4
125
125
3.3V
Z_o = 50
+
Z_o = 50
R1
84
_
R2
84
Input
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
843751 REVISION B 08.21.15
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