IDT723624 Datasheet, PDF (19/35 Pages) Integrated Device Technology – CMOS SyncBiFIFOTM WITH BUS-MATCHING

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA
tCLKH
tCLK
tCLKL
COMMERCIAL TEMPERATURE RANGE
FFA/IRA HIGH
CSA
W/RA
MBA
ENA
A0 - A35
NOTE:
1. Written to FIFO1.
tENS1
tENS1
tENH
tENH
tENS2
tENH
tENS2
tENH
tDS
tDH
W1⁽¹⁾
tENS2
tENH
W2 ⁽¹⁾
tENS2
tENH
No Operation
3270 drw09
Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKB
tCLKH
tCLK
tCLKL
FFB/IRB HIGH
CSB
W/RB
MBB
ENB
B0-B35
tENS1
tENH
tENS1
tENS2
tENH
tENH
tENS2
tENH
tDS
tDH
W1⁽¹⁾
NOTE:
1. Written to FIFO2.
tENS2
tENH
W2 ⁽¹⁾
tENS2
tENH
No Operation
3270 drw10
DATA SIZE TABLE .OR LONG-WORD WRITES TO .I.O2
SIZE MODE⁽¹⁾
BM
SIZE
BE
DATA WRITTEN TO FIFO2
B35-B27 B26-B18
B17-B9
B8-B0
DATA READ FROM FIFO2
A35-A27
A26-A18
A17-A9
L
X
X
A
B
C
D
A
B
C
NOTE:
1. BE is selected at Master Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
A8-A0
D
19