IDT723624 Datasheet, PDF (1/35 Pages) Integrated Device Technology – CMOS SyncBiFIFOTM WITH BUS-MATCHING

CMOS SyncBiFIFO^TM WITH BUS-MATCHING
256 x 36 x 2,
512 x 36 x 2,
1,024 x 36 x 2
IDT723624
IDT723634
IDT723644
.EATURES:
• Memory storage capacity:
IDT723624 – 256 x 36 x 2
IDT723634 – 512 x 36 x 2
IDT723644 – 1,024 x 36 x 2
• Clock frequencies up to 83 MHz (8 ns access time)
• Two independent clocked FIFOs buffering data in opposite
directions
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36-bits (long word), 18-bits (word) and
9-bits (byte)
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
.UNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
36
MBF2
Mail 1
Register
36
RAM ARRAY
256 x 36
36
512 x 36
1,024 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
10
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 256 x 36
36
512 x 36
1,024 x 36
Mail 2
Register
IDT, the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
 2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MBF1
36
EFB/ORB
AEB
36
FIFO2,
Mail2
Reset
Logic
FWFT
B0-B35
FFB/IRB
AFB
MRS2
PRS2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
3270 drw01
AUGUST 2001
DSC-3270/2