ICS951464 Datasheet, PDF (19/24 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems

ICS951464
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
RESET_IN# - Assertion (transition from '1' to '0')
Asserting RESET_IN pin stops all the outputs including CPU, SRC, ATIG, PCI and USB with the REF[2:0] running.
The pin is a Schmitt trigger input with debouncing. After it is triggered, REF clocks will wait for two clock cycle to
ensure the RESET_IN is asserted. Then, it will take 3uS for the clocks to stop without glitches. The clock chip will
be power down and re-power up, and SMBus will be reloaded. It will take no more than 2.5mS for the clocks to come
out with correct frequencies and no glitches.
** Deassertion of RESET_IN# (transition from '0' to '1') has NO effect on the clocks.
RESET_IN#
REF [2:0]
*CLKS
2 clock
cycles
3 uS max
2.5mS max
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
19
1211B—09/17/09