ADC1015S Datasheet, PDF (19/40 Pages) NXP Semiconductors – Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Preliminary data sheet

Integrated Device Technology
ADC1015S series
Single 10-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
package
ESD
8
INP
7
INM
INPUT
BUFFER
parasitics
switch
Ron = 15 Ω
4 pF
internal
clock
sampling
capacitor
switch
Ron = 15 Ω
4 pF
internal
clock
sampling
capacitor
Fig 14. Input sampling circuit and input buffer
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The integrated input buffer offers the following advantages:
• The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there’s no need for additional
filtering.
• The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1015S easy to drive.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 15 would be suitable for a baseband application.
ADC1015S_SER 3
Product data sheet
ADT1-1WT
Analog ^{100 nF}
input
100 nF
100 nF
INP
100 nF
50 Ω
100 nF
INM
VCM
100 nF
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Fig 15. Single transformer configuration suitable for baseband applications
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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