ADC1015S Datasheet, PDF (1/40 Pages) NXP Semiconductors – Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Preliminary data sheet

ADC1015S series
Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
with input buffer; CMOS or LVDS DDR digital outputs
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The ADC1015S is a single channel 10-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1015S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
because of a separate digital output supply.
The ADC1015S supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1015S is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications because of the integrated input buffer. The input buffer
ensures that the input impedance remains constant and low and the performance
consistent over a wide frequency range.
2. Features and benefits
 SNR, 61.7 dBFS / SFDR, 86 dBc
 Sample rate up to 125 Msps
 10-bit pipelined ADC core
 Clock input divided by 2 for less jitter
contribution
 Integrated input buffer
 Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
 CMOS or LVDS DDR digital outputs
 Pin compatible with the ADC1415S
series, the ADC1215S series and the
ADC1115S125
 Input bandwidth, 600 MHz
 Power dissipation, 635 mW at 80 Msps,
including analog input buffer
 Serial Peripheral Interface (SPI)
 Duty cycle stabilizer
 Fast OuT-of-Range (OTR) detection
 Offset binary, two’s complement, gray
code
 Power-down mode and Sleep mode
 HVQFN40 package
®