IDT82P2821_09 Datasheet, PDF (18/151 Pages) Integrated Device Technology – nul21(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2821
2 PIN DESCRIPTION
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Name
RTIPn
RRINGn
(n=0~21)
TTIPn
TRINGn
(n=0~21)
I/O
Input
Output
Pin No. ¹
Description
Line Interface
P3, R5, V4, W5, AA4, AB5, AE28, RTIPn / RRINGn: Receive Bipolar Tip/Ring for Channel 0 ~ 21
AE26, AA26, W28, T28, R26, L28, The receive line interface supports both Receive Differential mode and Receive Single Ended
L26, G26, F28, D6, D4, D3, G4, H5, mode.
M5
In Receive Differential mode, the received signal is coupled into RTIPn and RRINGn via a 1:1
transformer or without a transformer (transformer-less).
N3, P5, U4, V5, Y4, AA5, AD28, In Receive Single Ended mode, RRINGn should be left open. The received signal is input on
AD26, Y26, W27, R28, P26, K28, RTIPn via a 2:1 (step down) transformer or without a transformer (transformer-less).
K26, F26, E28, E6, D5, E3, F4, G5, These pins will become High-Z globally or channel specific in the following conditions:
L5
• Global High-Z:
- Connecting the RIM pin to low;
- Loss of MCLK
- During and after power-on reset, hardware reset or global software reset;
• Per-channel High-Z
- Receiver power down by writing ‘1’ to the R_OFF bit (b5, RCF0,...)
L1, M1, R1, U1, Y1, AA1, AF30, TTIPn / TRINGn: Transmit Bipolar Tip /Ring for Channel 0 ~ 21
AD30, AA30, W30, T30, P30, L30, The transmit line interface supports both Transmit Differential mode and Transmit Single
J30, F30, D30, A5, A4, A3, C1, F1, Ended mode.
J1
In Transmit Differential mode, TTIPn outputs a positive differential pulse while TRINGn out-
puts a negative differential pulse. The pulses are coupled to the line side via a 1:2 (step up)
K1, M2, R2, T1, W1, AA2, AE30, transformer or without a transformer (transformer-less).
AC30, Y30, V30, R30, N30, K30, In Transmit Single Ended mode, TRINGn should be left open (it is shorted to ground inter-
H30, E30, C30, A6, B4, B3, D1, E1, nally). The signal presented at TTIPn is output to the line side via a 1:2 (step up) transformer.
J2
These pins will become High-Z globally or channel specific in the following conditions:
• Global High-Z:
- Connecting the OE pin to low;
- Loss of MCLK;
- During and after power-on reset, hardware reset or global software reset;
• Per-channel High-Z
- Writing ‘0’ to the OE bit (b6, TCF0,...) ²;
- Loss of TCLKn in Transmit Single Rail NRZ Format mode or Transmit Dual Rail NRZ
Format mode, except that the channel is in Remote Loopback or transmit internal pat-
tern with XCLK ³;
- Transmitter power down by writing ‘1’ to the T_OFF bit (b5, TCF0,...);
- Per-channel software reset;
- The THZ_OC bit (b4, TCF0,...) is set to ‘1’ and the transmit driver over-current is
detected.
Refer to Section 3.3.8 Output High-Z on TTIP and TRING for details.
Note:
1. The pin number of the pins with the footnote ‘n’ is listed in order of channel (CH0 ~ CH21).
2. The content in the brackets indicates the position and the register name of the preceding bit. After the register name, if the punctuation ‘,...’ is followed, this bit is in a per-channel register.
If there is no punctuation following the address, this bit is in a global register or in a channel 0 only register. The addresses and details are included in Chapter 5 Programming Information.
3. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz in E1 mode.
Pin Description
18
February 6, 2009