IDT82P2821_09 Datasheet, PDF (142/151 Pages) Integrated Device Technology – nul21(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
8.13.4 PARALLEL MOTOROLA MULTIPLEXED MICROPROCESSOR INTERFACE
8.13.4.1Read Cycle Specification
Symbol
t_ASW
t_RSW
t_CSD
t_RWV
t_RWH
t_VAS
t_VAH
t_PRD
t_ZRD
Parameter
Min
MAX
Units
Valid AS signal width
Valid read signal width
5
ns
41 (T1/J1) / 38 (E1) or wait until ACK activated
ns
Valid DS + CS falling edge delay after AS
0
ns
R/W available time after valid DS + CS signal falling edge
0
ns
R/W hold time after valid DS + CS signal falling edge
36 (T1/J1) / 33 (E1)
ns
Valid address to AS setup time
5
ns
Valid address to AS hold time
5
ns
Data propagation delay after valid DS + CS signal falling edge
36 (T1/J1) / 33 (E1) ns
Valid read negated to output High-Z before valid AS rising
5
edge
20
ns
DS + CS
R/W
AS
D[7:0]
ACK
tASW
tCSD
tVAS
Valid address
tVAH
tRSW
tRWH
tRWV
tPRD
tZRD
Valid Data
Figure-65 Parallel Motorola Multiplexed Microprocessor Interface Read Cycle
Physical And Electrical Specifications
142
February 6, 2009