IDT70V7589S Datasheet, PDF (18/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V7589S
High-Speed 64K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)^(1,6)
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
INTERNAL⁽³⁾
ADDRESS
ADS
CNTEN
DATAIN
tSAD tHAD
An⁽⁵⁾
An + 1
An + 2
An + 3
An + 4
tSCN tHCN
tSD tHD
Dn
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 1
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
Dn + 3
Dn + 4
WRITE WITH COUNTER
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Timing Waveform of Counter Repeat for Flow Through Mode^(2,6,7)
tCYC2
CLK
tSA tHA
ADDRESS
An
INTERNAL⁽³⁾
ADDRESS
An
An+1
An+2
An+2
An
An+1
An+2
An+2
ADS
tSAD tHAD
R/W
tSW tHW
CNTEN
tSCN tHCN
(4)
REPEAT
tSRPT tHRPT
tSD tHD
DATAIN
D0
D1
D2
D3
tCD1
DATAOUT
An
An+1
An+2
An+2
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
An+1
,
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
NOTES:
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1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.
7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.1482