IDT70V7589S Datasheet, PDF (11/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V7589S
High-Speed 64K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)⁽²⁾ (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V 7589S 200 ⁽⁵⁾
Com'l Only
70V 7589S 166 ^{(3,4 )}
C o m 'l
& Ind
70V 7589S 133⁽³⁾
C o m 'l
& Ind
Symbol
tCY C1
tCY C2
tC H 1
tCL 1
tC H 2
tCL 2
tR
tF
tS A
tH A
tS C
tH C
Clo ck Cycle Time (Flo w-Thro ug h)⁽¹⁾
Clo ck Cycle Time (P ip e line d)⁽¹⁾
Clo ck Hig h Time (Flo w-Thro ug h)⁽¹⁾
Clo ck Lo w Tim e (Flow-Thro ugh)⁽¹⁾
Clo ck Hig h Time (P ip e line d)⁽²⁾
Clo ck Lo w Tim e (P ipe line d )⁽¹⁾
Clock Rise Time
Clock Fall Time
Address Se tup Tim e
Address Hold Tim e
Chip E nab le S e tup Time
Chip Enable Hold Time
P aram eter
Min. Max. Min. Max. Min. Max. Unit
15
____
20
____
25
____
ns
5
____
6
____
7.5
____
ns
5
____
6
____
7
____
ns
5
____
6
____
7
____
ns
2.0
____
2.1
____
2.6
____
ns
2.0
____
2.1
____
2.6
____
ns
____
1.5
____
1.5
____
1.5
ns
____
1.5
____
1.5
____
1.5
ns
1.5
____
1.7
____
1.8
____
ns
0.5
____
0.5
____
0.5
____
ns
1.5
____
1.7
____
1.8
____
ns
0.5
____
0.5
____
0.5
____
ns
tS W
R/W S e tup Time
1.5
____
1.7
____
1.8
____
ns
tH W
R/W Hold Time
0.5
____
0.5
____
0.5
____
ns
tS D
Inp ut Data S e tup Time
tH D
Input Data Ho ld Tim e
tSA D
ADS S e tup Time
tHA D
ADS Ho ld Time
tSC N
CNTEN S e tup Time
tHC N
CNTEN Ho ld Time
tS RP T
REPEAT S e tup Time
tHRP T
REPEAT Ho ld Time
tOE
Outp ut Enab le to Data Valid
tOL Z
Outp ut Enab le to Outp ut Lo w-Z
1.5
____
1.7
____
1.8
____
ns
0.5
____
0.5
____
0.5
____
ns
1.5
____
1.7
____
1.8
____
ns
0.5
____
0.5
____
0.5
____
ns
1.5
____
1.7
____
1.8
____
ns
0.5
____
0.5
____
0.5
____
ns
1.5
____
1.7
____
1.8
____
ns
0.5
____
0.5
____
0.5
____
ns
____
4.0
____
4.0
____
4.2
ns
0.5
____
0.5
____
0.5
____
ns
tO HZ
Outp ut Enab le to Outp ut Hig h-Z
tC D 1
Clo ck to Data Valid (Flo w-Thro ug h)⁽¹⁾
tC D 2
Clo ck to Data Valid (Pip e lined )⁽¹⁾
tD C
Data Output Ho ld A fte r Clo ck Hig h
1
3.4
1
3.6
1
4.2 ns
____
10
____
12
____
15
ns
____
3.4
____
3.6
____
4.2
ns
1
____
1
____
1
____
ns
tCK HZ
Clo ck Hig h to Outp ut Hig h-Z
1
3.4
1
3.6
1
4.2 ns
tC KL Z
Clo ck Hig h to Outp ut Lo w-Z
0.5
____
0.5
____
0.5
____
ns
Port-to-Port Delay
tCO
Clo ck-to -Clo ck Offse t
5.0
____
6.0
____
7.5
____
ns
NOTES:
5 627 tb l 11
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPEX = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
4. 166MHz Industrial Temperature not available in BF-208 package.
5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only.
6.1412