IDT70V3319 Datasheet, PDF (18/23 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)⁽¹⁾
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
INTERNAL⁽³⁾
ADDRESS
ADS
CNTEN
DATAIN
An⁽⁷⁾
tSAD tHAD
An + 1
An + 2
An + 3
An + 4
tSCN tHCN
tSD tHD
Dn
Dn + 1
Dn + 1
Dn + 2
WRITE
EXTERNAL
ADDRESS
WRITE
WRITE
WITH COUNTER COUNTER HOLD
Dn + 3
Dn + 4
WRITE WITH COUNTER
5623 drw 18
Timing Waveform of Counter Repeat⁽²⁾
tCYC2
tCH2
tCL2
CLK
ADDRESS
INTERNAL⁽³⁾
ADDRESS
Ax
R/W
LAST ADS LOAD
tSW tHW
tSA tHA
An
(4)
An + 1
An + 2
LAST ADS +1
An
An + 1
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRPT tHRPT
REPEAT
tSD tHD
DATAIN
D0
(5)
DATAOUT
QLAST
QLAST+1
Qn
(6)
EXECUTE
REPEAT
WRITE
LAST ADS
READ
LAST ADS
READ
LAST ADS
READ
READ
ADDRESS n ADDRESS n+1
ADDRESS
ADDRESS ADDRESS + 1
5623 drw 19
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
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