IDT70V3319 Datasheet, PDF (1/23 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 3.3V
256/128K x 18
SYNCHRONOUS
IDT70V3319/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
– Due to limited pin count PL/FT option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
Functional Block Diagram
UBL
LBL
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output mode}
◆ _{LVTTL- compatible, single 3.3V (±150mV) power supply}
for core
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 133MHz.
◆ _{Available in a 128-pin Thin Quad Flatpack, 208-pin fine}
pitch Ball Grid Array, and 256-pin Ball
Grid Array
◆ _{Supports JTAG features compliant to IEEE 1149.1}
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
UBR
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
a
b
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Do ut9-17_R
1b 0b
b
1a 0a
1/0
a
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
256K x 18
MEMORY
ARRAY
0a 1a 0b 1b
0/1
ba
,
FT/PIPER
I/O0L - I/O17L
CLKL
A17 L(1)
A0L
REPEATL
ADSL
CNTENL
NOTE:
1. A17 is a NC for IDT70V3399.
Counter/
Address
Reg.
TDI
TDO
©2003 Integrated Device Technology, Inc.
Din_L
Din_R
ADDR_L
ADDR_R
JTAG
1
Counter/
Address
Reg.
TCK
TMS
TRST
I/O0R - I/O17R
CLKR
A17R(1)
A0R
REPEATR
ADSR
CNTENR
,
5623 tbl 01
MAY 2003
DSC 5623/7