IDT723622_15 Datasheet, PDF (17/24 Pages) Integrated Device Technology – CMOS SyncBiFIFO

IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
CSB LOW
W/RB ^LOW
MBB
ENB
tENS2
tENS2
tENH
tENH
tCLKH
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKL
IRB HIGH
tDS
tDH
B0 - B35
CLKA
W1
(1)
tSKEW1
tCLK
tCLKH tCLKL
1
2
ORA FIFO2 Empty
3
tPOR
tPOR
CSA LOW
W/RA LOW
MBA LOW
tENS2
tENH
ENA
tA
A0-A35
Old Data in FIFO2 Output Register
W1
3022 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
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