IDT723622_15 Datasheet, PDF (1/24 Pages) Integrated Device Technology – CMOS SyncBiFIFO

CMOS SyncBiFIFO^TM
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT723622
IDT723632
IDT723642
FEATURES:
• Memory storage capacity:
IDT723622 – 256 x 36 x 2
IDT723632 – 512 x 36 x 2
IDT723642 – 1,024 x 36 x 2
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Two independent clocked FIFOs buffering data in opposite
directions
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA, and AFA flags synchronized by CLKA
• IRB, ORB, AEB, and AFB flags synchronized by CLKB
• Supports clock frequencies up to 66.7MHz
• Fast access times of 10ns
• Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
• Green parts available
DESCRIPTION:
The IDT723622/723632/723642 are a monolithic, high-speed, low-power,
CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre-
quencies up to 66.7MHz and have read access times as fast as 10ns.
Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board
each chip buffer data in opposite directions. Communication between
each port may bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
MBF1
36
IRA
AFA
FIFO 1
Status Flag
Logic
ORB
AEB
FS0
FS1
A0 - A35
ORA
AEA
36
Programmable Flag
Offset Registers
10
FIFO 2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
B0 - B35
IRB
AFB
36
FIFO2,
Mail2
Reset
Logic
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
3022 drw 01
FEBRUARY 2015
DSC-3022/6