IDT70T651 Datasheet, PDF (17/27 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
Parameter
70T651/9S8⁽⁶⁾
70T651/9S10
70T651/9S12
70T651/9S15
Com'l Only
Com'l
& Ind⁽⁶⁾
Com'l
& Ind
Com'l Only
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
8
____
10
____
12
____
15
ns
tBDA
BUSY Disable Time from Address Not Matched
____
8
____
10
____
12
____
15
ns
tBAC
BUSY Access Time from Chip Enable Low
____
8
____
10
____
12
____
15
ns
tBDC
BUSY Disable Time from Chip Enable High
____
8
____
10
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time⁽²⁾
2.5
____
2.5
____
2.5
____
2.5
____
ns
tBDD
BUSY Disable to Valid Data⁽³⁾
tWH
Write Hold After BUSY⁽⁵⁾
BUSY TIMING (M/S=VIL)
____
8
____
10
____
12
____
15
ns
6
____
7
____
9
____
12
____
ns
tWB
BUSY Input to Write⁽⁴⁾
tWH
Write Hold After BUSY⁽⁵⁾
0
____
0
____
0
____
0
____
ns
6
____
7
____
9
____
12
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay⁽¹⁾
tDDD
Write Data Valid to Read Data Delay⁽¹⁾
____
12
____
14
____
16
____
20
ns
____
12
____
14
____
16
____
20
ns
NOTES:
5632 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range^(1,2,3)
Symbol
Parameter
70T651/9S8⁽⁴⁾
Com'l Only
Min. Max.
70T651/9S10
Com'l
& Ind⁽⁴⁾
Min. Max.
70T651/9S12
Com'l
& Ind
Min. Max.
70T651/9S15
Com'l Only
Min. Max.
SLEEP MODE TIMING (ZZx=VIH)
tZZS
Sleep Mode Set Time
8
____
10
____
12
____
15
____
tZZR
Sleep Mode Reset Time
tZZPD
Sleep Mode Power Down Time⁽⁵⁾
tZZPU
Sleep Mode Power Up Time⁽⁵⁾
8
____
10
____
12
____
15
____
8
____
10
____
12
____
15
____
____
0
____
0
____
0
____
0
NOTES:
5632 tbl 15a
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
5. This parameter is guaranteed by device characterization, but is not production tested.
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