IDT70T651 Datasheet, PDF (1/27 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY
IDT70T651/9S
Features
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed access}
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
◆ _{RapidWrite Mode simplifies high-speed consecutive write}
cycles
◆ _{Dual chip enables allow for depth expansion without}
external logic
◆ _{IDT70T651/9 easily expands data bus width to 72 bits or}
more using the Master/Slave select when cascading more
than one device
◆ _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
◆ _{Busy and Interrupt Flags}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Sleep Mode Inputs on both ports}
◆ _{Supports JTAG features compliant to IEEE 1149.1}
◆ _{Single 2.5V (±100mV) power supply for core}
◆ _{LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)}
power supply for I/Os and control signals on each port
◆ _{Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad}
Flatpack and 208-ball fine pitch Ball Grid Array.
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
R/WL
CE0L
C E1L
BB BB BBBB
EE EE EEEE
01 23 3210
L L L L RRRR
BE 3R
BE2R
BE 1R
BE0R
R/WR
CE0R
CE1R
OEL
I/O0L- I/O35L
Dout0-8_L Dout0-8_R
Dout9-17_L _{Dout9-17_R}
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
256/128K x 36
MEMORY
ARRAY
Di n_L
Di n_R
OER
I/O0R -I/O35R
A17L(1)
A0L
Address
Decoder
ADDR_L ADDR_R
Address
Decoder
A17R(1)
A0R
BUSYL(2,3)
SEML
INTL(3)
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CE0R
TDI
TC K
CE1R
JTAG
TMS
OER
TD O
TRST
R/WR
BUSYR(2,3)
SEMR
INTR(3)
NOTES:
ZZL(4)
ZZ
CO NT RO L
LOGIC
ZZR(4)
1. Address A17x is a NC for IDT70T659.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4869 drw 01
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep
mode pins themselves (ZZx) are not affected during sleep mode.
NOVEMBER
2003
1
©2003 Integrated Device Technology, Inc.
DSC-5632/3