ICS810001-22 Datasheet, PDF (16/18 Pages) Integrated Device Technology – FemtoClock™ Dual VCXO Video PLL

ICS810001-22 Data Sheet
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
Ind exArea
N
To p View
S eating Plan e
A1
A_An_nv_vi_il_l
Si_Sn_ig_ngu_ula_lati_to_ion_n
or
Sa^Ow^Rn
Singulation
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
N
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
(Ref.)
N &N
Even
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
b
Th er mal
Ba se
Bottom View w/Type A ID
Bottom View w/Type B ID
Bottom View w/Type C ID
4
2
1
CHAMFER
4
N N-1
There are 3 methods of indicating pin 1 corner
4
at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
3. Type C: Mouse bite on the paddle (near pin 1)
Table 7. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
N_D & N_E
D&E
8
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS810001BK-22 REVISION A SEPTEMBER 8, 2009
2
1
DD
4
N N-1
AA
4
2
1
RADIUS
4
N N-1
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 7 below.
16
©2009 Integrated Device Technology, Inc.