ICS810001-22 Datasheet, PDF (11/18 Pages) Integrated Device Technology – FemtoClock™ Dual VCXO Video PLL

ICS810001-22 Data Sheet
Application Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS810001-22 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_DD, V_DDA, V_DDO and V_DDX should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V_DD pin and also shows that V_DDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the V_DDA pin.
V_DD
VDDX
3.3V
.01µF
10Ω
10Ω
.01µF 10µF
VDDA
.01µF 10µF
Figure 1. Power Supply Filtering
ICS810001BK-22 REVISION A SEPTEMBER 8, 2009
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©2009 Integrated Device Technology, Inc.