IDT71P72204 Datasheet, PDF (15/22 Pages) Integrated Device Technology – 18Mb Pipelined QDRII SRAM Burst of 2

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
Advance Information
18 Mb QDR II SRAM Burst of 2
Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry
when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the
SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that
resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable
the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI
are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
SA,D
K,K
C,C
Q
CQ
CQ
TDI
TMS
TCK
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TA P Controller
TDO
6109 drw 18
TAP Controller State Diagram
Test Logic Reset
1
0
Run Test Idle ¹
0
Select DR ¹
0
1 _{Capture DR}
0
Shift DR
0
1
1
Exit 1 DR
0
Pause DR
0
1
Exit 2 DR
0
1
1 _{Update DR}
0
Select IR
1
0
1 _{Capture IR}
0
Shift IR
0
1
1 _{Exit 1 IR}
0
Pause IR
0
1
Exit 2 IR
0
1
Update IR
0
1
6109 drw 17
JTAG Instruction Coding
IR2 IR1 IR0
Instruction TDO Output
Notes
000
EXTEST
Boundary Scan Register
00 1
IDCODE
Identification register
2
0 10
SAMPLE-Z Boundary Scan Register 1
011
RESERVED Do Not Use
5
1 0 0 SAMPLE/PRELOAD Boundary Scan register 4
10 1
RESERVED Do Not Use
5
110
RESERVED Do Not Use
5
111
BYPASS
Bypass Register
3
NOTES:
6109tbl 13
1. Places Qs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
3. Bypass register is initialized to Vss when BYPASS instruction is invoked.
The Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
61.452