IDT71P72204 Datasheet, PDF (1/22 Pages) Integrated Device Technology – 18Mb Pipelined QDRII SRAM Burst of 2

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18Mb Pipelined
QDR™II SRAM
Burst of 2
Information
IDT71P72204
IDT71P72104
IDT71P72804
Features
Description
IDT71P72604
x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
The IDT QDRII^TM Burst of two SRAMs are high-speed synchronous
x Separate, Independent Read and Write Data Ports
memories with independent, double-data-rate (DDR), read and write
- Supports concurrent transactions
data ports. This scheme allows simultaneous read and write access for
x Dual Echo Clock Output
the maximum device throughput, with two data items passed with each
x 2-Word Burst on all SRAM accesses
read or write. Four data word transfers occur per clock cycle, providing
x DDR (Double Data Rate) Multiplexed Address Bus
quad-data-rate (QDR) performance. Comparing this with standard SRAM
- One Read and One Write request per clock cycle common I/O (CIO), single data rate (SDR) devices, a four to one in-
x DDR (Double Data Rate) Data Buses
crease in data access is achieved at equivalent clock speeds. Consider-
- Two word burst data per clock on each port
ing that QDRII allows clock speeds in excess of standard SRAM de-
- Four word transfers per clock cycle (2 word
vices, the throughput can be increased well beyond four to one in most
bursts on 2 ports)
applications.
x Depth expansion through Control Logic
Using independent ports for read and write data access, simplifies
x HSTL (1.5V) inputs that can be scaled to receive signals system design by eliminating the need for bi-directional buses. All buses
from 1.4V to 1.9V.
associated with the QDRII are unidirectional and can be optimized for
x Scalable output drivers
signal integrity at very high bus speeds. The QDRII has scalable output
- Can drive HSTL, 1.8V TTL or any voltage level impedance on its data output bus and echo clocks, allowing the user to
from 1.4V to 1.9V.
tune the bus for low noise and high performance.
- Output Impedance adjustable from 35 ohms to 70
The QDRII has a single DDR address bus with multiplexed read and
ohms
write addresses. All read addresses are received on the first half of the
x 1.8V Core Voltage (VDD)
clock cycle and all write addresses are received on the second half of the
x 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
clock cycle. The read and write enables are received on the first half of
x JTAG Interface
the clock cycle. The byte and nibble write signals are received on both
halves of the clock cycle simultaneously with the data they are controlling
on the data input bus.
The QDRII has echo clocks, which provide the user with a clock
Functional Block Diagram
(Note1)
D
DATA
REG
DATA
REG
(Note1)
(Note1)
SA ^(Note2)
ADD
REG
(Note2)
R
W
CTRL
(Note3) LOGIC
BWx
WRITE DRIVER
18M
MEMORY
ARRAY
(Note4)
(Note4)
(Note1) _Q
Notes
K
CLK
CQ
K
GEN
CQ
C
SELECT OUTPUT CONTROL
C
6109 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6109/0C