ICS853S006I Datasheet, PDF (15/19 Pages) Integrated Device Technology – One differential PCLK

ICS853S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S006I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S006I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 60mA = 207.9mW
• Power (outputs)_MAX = 32.02mW
If all outputs are loaded, the total power is 6 * 32.02mW = 192.12mW
Total Power__MAX (3.465V, with all outputs switching) = 207.9mW + 192.12mW = 400.02mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for this device is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C
ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.400W * 92.1°C/W = 121.84°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θ_JA for 20 Lead TSSOP, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
92.1°C/W
1
86.5°C/W
2.5
83.0°C/W
ICS853S006AGI REVISION A NOVEMBER 15, 2011
15
©2011 Integrated Device Technology, Inc.