ICS853S006I Datasheet, PDF (14/19 Pages) Integrated Device Technology – One differential PCLK

ICS853S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Schematic Example
Figure 6 shows a schematic example of ICS853S006I. The
ICS853S006I input can accept various types of differential input
signal. In this example, the inputs are driven by an LVPECL drivers.
For the ICS853S006I LVPECL output driver, an example of LVPECL
driver termination approach is shown in this schematic. Additional
LVPECL driver termination approaches are shown in the LVPECL
Termination Application Note. It is recommended at least one
decoupling capacitor per power pin. The decoupling capacitors
should be physically located near the power pins. For ICS853S006I,
the unused output can be left floating.
Zo = 50
Zo = 50
3.3V
3.3V
Zo = 50
Zo = 50
3.3V LVPECL
R9
R10
50
50
R11
C7(Optional)
50
0.1u
U1
1
2
3
4
VCC
nQ0
Q0
5
6
7
nQ1
Q1
nQ2
8 ^Q2
9
10
VCC
PCLK
nPCLK
ICS853006
VCC
Q5
nQ5
20
19
18
17
Q4
nQ4
Q3
16
15
14
nQ3 ₁₃
VCC
VEE
VBB
12
11
3.3V
Zo = 50
Zo = 50
(U1, 1)
(U1, 8)
3.3V
(U1, 13)
(U1, 20)
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
+
-
R2
R1
50
50
R3
C5 (Optional)
50
0.1u
+
-
R5
R4
50
50
R6
C6 (Optional)
50
0.1u
Figure 6. ICS853S006I Example LVPECL Clock Output Buffer Schematic
ICS853S006AGI REVISION A NOVEMBER 15, 2011
14
©2011 Integrated Device Technology, Inc.