IDT723626_14 Datasheet, PDF (14/35 Pages) Integrated Device Technology – CMOS TRIPLE BUS SyncFIFO

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC) function is selected. In IDT Standard mode, the Full Flag (FFA and FFC)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time a
word is written to a FIFO, its write pointer is incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH transition
on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input
Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing
clock begins the first synchronization cycle of a read if the clock transition
occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent
clock cycle can be the first synchronization cycle (see Figures 20, 21, 22,
and 23).
ALMOST-EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see Almost-Empty flag
and Almost-Full flag offset programming section). An Almost-Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its FIFO contains
(X+1) or more words. A data word present in the FIFO output register has been
read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clock are required after a FIFO write for its Almost-Empty flag to reflect the
new level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1)
or more words remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty
flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock
after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1)
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figures 24 and 25).
ALMOST-FULL FLAGS (AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the port clock that
writes data to its array. The state machine that controls an Almost-Full flag
monitors a write pointer and read pointer comparator that indicates when
the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The
almost-full state is defined by the contents of register Y1 for AFA and register Y2
for AFC. These registers are loaded with preset values during a FlFO reset,
programmed from Port A, or programmed serially (see Almost-Empty flag and
Almost-Full flag offset programming section). An Almost-Full flag is LOW when
the number of words in its FIFO is greater than or equal to (256-Y), (512-Y),
or (1,024-Y) for the IDT723626, IDT723636, or IDT723646 respectively. An
Almost-Full flag is HIGH when the number of words in its FIFO is less than or
equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723626,
IDT723636, or IDT723646 respectively. Note that a data word present in the
FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)] or
less words remains LOW if two cycles of its synchronizing clock have not elapsed
since the read that reduced the number of words in memory to [256/512/1,024-
(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition
of its synchronizing clock after the FIFO read that reduces the number of words
in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-
Full flag synchronizing clock begins the first synchronization cycle if it occurs at
time tSKEW2 or greater after the read that reduces the number of words in
memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchronizing
clock cycle may be the first synchronization cycle (see Figures 26 and 27).
MAILBOX REGISTERS
Each FIFO has an 18-bit bypass register allowing the passage of
command and control information from Port A to Port B or from Port C to Port
A without putting it in queue. The Mailbox Select (MBA, MBB and MBC) inputs
choose between a mail register and a FIFO for a port data transfer operation.
The usable width of both the Mail1 and Mail2 registers matches the selected bus
size for ports B and C.
When sending data from Port A to Port B via the Mail1 Register, the
following is the case: A LOW-to-HIGH transition on CLKA writes data to the Mail1
Register when a Port A write is selected by CSA, W/RA, and ENA with MBA
HIGH. If the selected Port B bus size is 18 bits, then the usable width of the Mail1
Register employs data lines A0-A17. (In this case, A18-A35 are don’t care
inputs.) If the selected Port B bus size is 9 bits, then the usable width of the Mail1
Register employs data lines A0-A8. (In this case, A9-A35 are don’t care inputs.)
When sending data from Port C to Port A via the Mail2 Register, the following
is the case: A LOW-to-HIGH transition on CLKC writes data to the Mail2 Register
when a Port C write is selected by WENC with MBC HIGH. If the selected Port
C bus size is 18 bits, then the usable width of the Mail2 Register employs data
lines C0-C17. If the selected Port C bus size is 9 bits, then the usable width of
the Mail2 Register employs data lines C0-C8. (In this case, C9-C17 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2)
LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port mailbox select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a Port B read is selected by CSB, and RENB with MBB HIGH.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. For the
9-bit bus size, 9 bits of mailbox data are placed on B0-B8. (In this case, B9-B17
are indeterminate.)
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read and changes only
when new data is written to the register. For an 18-bit bus size, 18 bits of mailbox
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