IDT723626_14 Datasheet, PDF (1/35 Pages) Integrated Device Technology – CMOS TRIPLE BUS SyncFIFO

CMOS TRIPLE BUS SyncFIFO^TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2
IDT723626
IDT723636
IDT723646
FEATURES:
• Memory storage capacity:
IDT723626 – 256 x 36 x 2
IDT723636 – 512 x 36 x 2
IDT723646 – 1,024 x 36 x 2
• Clock frequencies up to 67 MHz (10ns access time)
• Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Green parts available, see ordering information
DESCRIPTION:
The IDT723626/723636/723646 is a monolithic, high-speed, low-power,
CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock
frequencies up to 67 MHz and has read access times as fast as 10 ns. Two
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
36
Mail 1
Register
36
RAM ARRAY
256 x 36
36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
FIFO1
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
10
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
MBF2
RAM ARRAY
36 _{256 x 36}
36
512 x 36
1,024 x 36
Mail 2
Register
MBF1
18
B0-B17
Port-B
Control
Logic
CLKB
RENB
CSB
MBB
SIZEB
Common
Port
Control
Logic
(B and C)
FIFO2,
Mail2
Reset
Logic
18
Port-C
Control
Logic
EFB/ORB
AEB
BE
FWFT
FFC/IRC
AFC
MRS2
PRS2
C0-C17
CLKC
WENC
MBC
SIZEC
3271 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2014
DSC-3271/6