9VRS4338D Datasheet, PDF (14/23 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4338D
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Electrical Characteristics–Input/Supply/Common Output Parameters
PARAMETER
Ambient Operating Temp
SYMBOL
Tamb ien t
VDD
C ON DITIONS
-
Supply Voltage
MIN
TYP
MAX UNITS Notes
0
25
85
°C
3. 135
3. 3
3.465
V
Supply Voltage
V DD_CORE_ 1.5
Supply Voltage
1. 425
1. 5
1.575
V
Input High Voltage
Input Low Voltage
Latched Input High Voltage
V DD_L VIO
V_{IH SE}
V ILS E
Supply Voltage
Single-ended 3.3V inputs
Single-ended 3.3V inputs
0.9 975
1.0 5
1.575
V
2
V_DD + 0.3
V
7
VSS - 0.3
0.8
V
7
VIH_ LI
Single-ended 3.3V Latched Inputs
2
VDD + 0.3 V
Latched Input Low Voltage
Low Threshold Latched Input-
High Voltage
Low Threshold Latched Input-
Low Voltage
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
V IL_LI
V_{IH _F S}
Single-ended 3.3V Latched Inputs
Low threshold inputs (FS(C:B))
VSS - 0.3
0 .7
0.8
V
VDD+0.3 V
V IL_F S
IIN
IIN RES
VOHS E
V O LS E
IDD OP3 .3
IDD OP1 .5
I DDOP1.0 5
Low threshold inputs (FS(C:B))
VIN = VDD , VIN = GND
Inputs with pull up or pull down
re si st ors
VIN = VDD , VIN = GND
Single-ended outputs, I_OH = -1mA
Single-ended outputs, IOL = 1 mA
Full Active, CL = Full load; IDD 3.3V
Full Active, CL = Full load; IDD 1.5V
Full Active, CL = Full load; IDD LVIO
VSS - 0.3
-5
-200
2 .4
17 .0
29 .5
31 .4
0.35
V
5
uA
6
2 00
uA
V
5
0.4
V
5
25
mA
35
mA
35
mA
Powerdown Current
Wake-On-Lan Current
Input Frequency
Pin Inductance
Input C apacitance
Clk Stabilization
Ts top_CR _off
Trun _CR_o n
Tsto p
Trun
Tf all _SE
Tri se _SE
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOLSMB = 0.4 V
SCLK /SD ATA
Clock/Data Rise Time
SCL K/S DATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequ enc y
Spread Spectrum Modulation
Frequ enc y
I_{DD PD3.3}
Power down mode, 3.3V Rail
IDD PD1.5
Power down mode, 1.5V Rail
I DDPD LVIO
Power down mode, 1.05V Rail
ID DW OL 3.3
Wake On Lan mode, 3.3V Rail
I_{D DW OL 1.5}
Wake On Lan mode, 1.5V Rail
IDD WOLLVIO
Wake On Lan mode, LVIO Rail
Fi
VDD = 3.3 V
Lpin
CIN
Logic Inputs
1 .5
C_{OU T}
Output pin capacitance
CIN X
X1 & X2 pins
TSTAB
From VDD Power-Up or de-assertion
of PD to 1st clock
TCR OFF
Output stop after CLKREQ#
de ass erted
2
TCRO N
Output run after CLKREQ# asserted
2
T _STOP
CPU or PCI stop after
CPU or PCI STOP# assertion
2
T_RUN
CPU or PCI run after
CPU or PCI STOP# de-assertion
2
TFALL
Fall/rise time of all 3.3V control inputs
TRISE
from 20-80%
V _DD
2 .7
V O LSMB
@ IPU LLUP
IPU LLUP
SMB Data Pin
4
T_{R I2C}
T_FI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
F_{SM BUS}
fSS MO D
Triangular Modulation
30
0. 3
0. 4
0. 0
4. 0
9. 0
0. 0
3. 3
31 .5
1
mA
9
1
mA
9
0.01
mA
9
5
mA
10
12
mA
10
0.01
mA
10
15
MHz
8
7
nH
5
pF
6
pF
6
pF
1.8
ms
3
Clocks
3
Clocks
3
Clocks
3
Clocks
10
ns
10
ns
3.6
V
0.4
V
mA
1 000
ns
3 00
ns
1 00
kHz
33
kH z
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 _{Intentionally blank}
2 _{Maximum VIH is not to exceed VDD}
3 _{Human Body Model}
4 _{Operation under these conditions is neither implied, nor guaranteed.}
5_{Signal is required to be monotonic in this region.}
6 _{Input leakage current does not include inputs with pull-up or pull-down resistors}
7 _{3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, ITP_EN, SCLK, SDATA, CLKPW RgD/PD#, SEL_PCI and CLKREQ# inputs if selected.}
8 _{For margining purposes only. Normal operation should have Fin = 14.318MHz +/-50ppm}
9 _{Standard powerdown with Wake on LAN disabled.}
10 _{Powerdown with Wake on LAN enabled}
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
14
9VRS4338D
REV A 022616