8V97051L Datasheet, PDF (14/57 Pages) Integrated Device Technology – Low Power Wideband Fractional RF Synthesizer / PLL

8V97051L Datasheet
In order to enable the fast lock mode, the charge pump current is
increased to the maximum value in order to increase the loop
bandwidth. In parallel, the FLSW filter is set to ON so that the RS
value is ¼ of its initial value in order to maintain the loop stability. By
doing so, the zero and the first pole are moved (by a factor of 4x in
the example below), so that the zero and the pole are kept at a
suitable distance around the loop bandwidth.
Table 4C. MUX_OUT Pin Configuration
MUX_OUT Register Value MUX_OUT Function
000
High-Impedance Output
001
V_DDD
010
GNDD
011
R Counter Output
100
N counter Output
101
Reserved
110
Lock Detect
111
MUX_OUT configured as SDO
Figure 8. Example of Fast Lock Mode Loop Filter
Topology
In the example of Figure 8, Example of Fast Lock Mode Loop Filter
Topology, the damping resistor RS is equal to:
RS1 + RS2 in normal mode (FSLW switch OFF), with RS2 = 3 * RS1
When the FLSW switch is ON, the damping resistor value is reduced
by ¼ of its initial value (RS = RS1).
The second pole defined by R3 and C3 need needs to be designed
so that there is no risk of instability when widening the loop
bandwidth.
RF Output Power
For RF_OUT_A and RF_OUT_B, the output power can be programmed
from -4dBm to +7dBm.
Refer to Table 9I, Page 26, Table 9K, Table 11E, Page 30 and Table
11F in the Register Map section for more information.
MUX_OUT
MUX_OUT is a multipurpose output that can be programmed to
provide the user with some internal status and values for test and
debugging purpose. In addition, MUX_OUT can also be programmed
to provide an additional Serial Data Out Pin for a 4-wire SPI interface
when needed. The MUX_OUT function is described in the Table 4C
and can be programmed in Bits[D28:D26] in Register 2.
Power-Down Mode
When power-down is activated, the following events occur:
1. Counters are forced to their load state conditions
2. VCO is powered down
3. Charge pump is forced into three-state mode
4. Digital lock detect circuitry is reset
5. RF_OUT buffers are disabled
6. The input stage is powered down and set to High-Impedance
7. Input registers remain active and capable of loading and
latching data
Default Power-Up Conditions
All the RF outputs are muted at power up until the loop is locked.
Refer to the Register Map section for default values in registers.
Program Modes
Table 4D and the Register Map indicate how the program modes are
set up in the 8V97051L.
Table 4D. Control Bits Configuration
Control Bits (CB)
C3
C2
C1
Register
0
0
0
Register 0
0
0
1
Register 1
0
1
0
Register 2
0
1
1
Register 3
1
0
0
Register 4
1
0
1
Register 5
1
1
0
Extended Register 6
1
1
1
Extended Register 7
©2017 Integrated Device Technology, Inc.
14
January 31, 2017