89HPES48T12 Datasheet, PDF (14/47 Pages) Integrated Device Technology – 48-Lane 12-Port PCI Express® Switch

IDT 89HPES48T12 Data Sheet
Logic Diagram — PES48T12
Reference
Clock
4
PEREFCLKP[3:0]
4
PEREFCLKN[3:0]
REFCLKM
PCI Express
Switch
SerDes Input
Port 0
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PE0TP[0]
PE0TN[0]
PE0TP[3]
PE0TN[3]
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Input
Port 1
PE1RP[0]
PE1RN[0]
PE1RP[3]
PE1RN[3]
PE1TP[0]
PE1TN[0]
PE1TP[3]
PE1TN[3]
PCI Express
Switch
SerDes Output
Port 1
PCI Express
Switch
SerDes Input
Port 2
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PE2TP[0]
PE2TN[0]
PE2TP[3]
PE2TN[3]
PCI Express
Switch
SerDes Output
Port 2
PCI Express
Switch
SerDes Input
Port 3
PE3RP[0]
PE3RN[0]
PE3RP[3]
PE3RN[3]
PE3TP[0]
PE3TN[0]
PE3TP[3]
PE3TN[3]
PCI Express
Switch
SerDes Output
Port 3
PCI Express
Switch
SerDes Input
Port 11
PE11RP[0]
PE11RN[0]
PE11RP[3]
PE11RN[3]
PES48T12
PE11TP[0]
PE11TN[0]
PE11TP[3]
PE11TN[3]
PCI Express
Switch
SerDes Output
Port 11
4
Master
SMBus Interface
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Slave
SMBus Interface
System
Pins
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
4
SWMODE[3:0]
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
P1011MERGEN
32
GPIO[31:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
V_DDCORE
V_DDIO
V_DDPE
V_DDPEA
V_SS
V_TTPE
General Purpose
I/O
JTAG Pins
Power/Ground
Figure 4 PES48T12 Logic Diagram
14 of 47
July 19, 2007