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89HPES48T12 Datasheet, PDF (1/47 Pages) Integrated Device Technology – 48-Lane 12-Port PCI Express® Switch | |||
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48-Lane 12-Port
PCI Express® Switch
®
89HPES48T12
Data Sheet
Device Overview
The 89HPES48T12 is a member of the IDT PRECISE⢠family of
PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
eleven downstream ports and supports switching between downstream
ports.
Features
â High Performance PCI Express Switch
â Twelve switch ports
⢠Six main ports each of which consists of 8 SerDes
⢠Each x8 main port can further bifurcate to 2 x4-ports
â Forty-eight 2.5 Gbps embedded SerDes
⢠Supports pre-emphasis and receive equalization on per-port
basis
â Delivers 192 Gbps (24 GBps) of aggregate switching capacity
â Low-latency cut-through switch architecture
â Support for Max Payload Size up to 2048 bytes
â Supports one virtual channel and eight traffic classes
â PCI Express Base Specification Revision 1.1 compliant
â Flexible Architecture with Numerous Configuration Options
â Port arbitration schemes utilizing round robin algorithms
â Automatic per port link width negotiation to x8, x4, x2 or x1
â Automatic lane reversal on all ports
â Automatic polarity inversion on all lanes
â Supports locked transactions, allowing use with legacy soft-
ware
â Ability to load device configuration from serial EEPROM
â Ability to control device via SMBus
â Highly Integrated Solution
â Requires no external components
â Incorporates on-chip internal memory for packet buffering and
queueing
â Integrates forty-eight 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
â Reliability, Availability, and Serviceability (RAS) Features
â Redundant upstream port failover capability
â Supports optional PCI Express end-to-end CRC checking
Block Diagram
Route Table
Frame Buffer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Upstream
12-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
x8/x4/x2/x1
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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July 19, 2007
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