IDT70V9269 Datasheet, PDF (13/15 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)⁽¹⁾
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
INTERNAL⁽³⁾
ADDRESS
ADS
tSAD tHAD
An⁽⁷⁾
An + 1
An + 2
An + 3
An + 4
CNTEN⁽⁷⁾
DATAIN
tSD tHD
Dn
Dn + 1
Dn + 1
Dn + 2
WRITE
EXTERNAL
ADDRESS
WRITE
WRITE
WITH COUNTER COUNTER HOLD
Dn + 3
Dn + 4
WRITE WITH COUNTER
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Timing Waveform of Counter Reset (Pipelined Outputs)⁽²⁾
tCYC2
tCH2
tCL2
CLK
ADDRESS
tSA tHA
An
(4)
An + 1
An + 2
INTERNAL⁽³⁾
ADDRESS
Ax⁽⁶⁾
R/W
0
tSW tHW
1
An
An + 1
ADS
CNTEN
tSRST tHRST
tSAD tHAD
tSCN tHCN
CNTRST
tSD tHD
DATAIN
D0
(5)
DATAOUT
Q0
Q1
Qn
COUNTER⁽⁶⁾
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
READ
ADDRESS n ADDRESS n+1
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
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3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An + 1’. The transition show indicates the time required for the counter to advance. The ‘An +1’ Address is
written to during this cycle.
6.1432