IDT70V9269 Datasheet, PDF (1/15 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 16K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9269S/L
Features:
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed clock to data access}
– Commercial: 9/12/15ns (max.)
x _{Low-power operation}
– IDT70V9269S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9269L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
x _{Flow-through or Pipelined output mode on either port via}
the FT/PIPE pin
x _{Counter enable and reset features}
x _{Dual chip enables allow for depth expansion without}
additional logic
x _{Full synchronous operation on both ports}
– 4ns setup to clock and 1ns hold on all Control,
data, and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in Pipelined output mode
x _{Separate upper-byte and lower-byte controls for}
multiplexed bus and bus matching compatibility
x _{LVTTL- compatible, single 3.3V (±0.3V) power supply}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
x _{Available in a 128-pin Thin Quad Flatpack (TQFP) package}
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
1
0
0/1
LBL
OEL
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
FT/PIPEL
I/O8L-I/O15L
0/1 ^{1b 0b} _{b a} ^{1a 0a}
I/O0L-I/O7L
A13L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
0a 1a _{a b0b} 1b _0/1
Counter/
Address
Reg.
FT/PIPER
I/O8R-I/O15R
I/O0R-I/O7R
A13R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3752 drw 01
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©2000 Integrated Device Technology, Inc.
JANUARY 2001
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