TSE2004GB2C0 Datasheet, PDF (12/38 Pages) Integrated Device Technology – DDR4 Temperature Sensor with Integrated 4Kbit EEPROM for Memory Module

I²C Bus Operating Modes
Table 4. I²C Bus Operating Modes
Mode
EE Current Address Read
EE Random Address Read
EE Sequential Read
EE Byte Write
EE Page Write
TS Write
TS Read
R/W_n Bit
1
0
1
1
0
0
0
1
Bytes
1
1
>1
1
<16
2
2
Device Reset and Initialization
Figure 7. V_DDSPD Ramp-up and Ramp-down
TSE2004GB2C0 Datasheet
Initial Sequence
START, Device Select, R/W_n = 1
START, Device Select, R/W_n = 0, Address
reSTART, Device Select, R/W_n = 1
Similar to Current or Random Address Read
START, Device Select, R/W_n = 0, data, STOP
START, Device Select, R/W_n = 0, data, STOP
START, Device Select, R/W_n = 0, pointer, data, STOP
START, Device Select, R/W_n = 1, pointer, data, STOP
In order to prevent inadvertent Write operations during power-up, a Power-On Reset (POR) circuit is included. To ensure proper startup
with cold power-on, V_DDSPD must rise monotonically between V_PON and V_DDSPD(min). Once V_DDSPD has passed the V_PON threshold, the
device is reset.
Prior to selecting the memory and issuing instructions, a valid and stable V_DDSPD voltage must be applied, and no command may be
issued to the device for t_INIT. This supply voltage must remain stable and valid until the end of the transmission of the instruction, and for
a Write instruction, until the completion of the internal Write cycle (t_W).
At Power-down (phase during which V_DDSPD decreases continuously), when V_DDSPD drops immediately below the minimum operating
voltage, the device stops responding to commands. On warm power cycling for t_POFF, V_DDSPD must remain below V_POFF, and must meet
cold power-on reset timing when restoring power.
The device is delivered with all bits in the EEPROM memory array when set to 1 (each byte contains 0xFF).
©2017 Integrated Device Technology, Inc.
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May 15, 2017