IDT70V27S_12 Datasheet, PDF (12/21 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
SEM
I/O
R/W
tAW
tWR
tEW
tDW
DATAIN VALID
tAS
tWP
tDH
tSOP
tACE
tOH
DATAOUT
VALID⁽²⁾
tSWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
3603 drw 09
Timing Waveform of Semaphore Write Contention^(1,3,4)
A0"A"-A2"A"
MATCH
SIDE⁽²⁾ _{“A”}
R/W"A"
SEM"A"
A0"B"-A2"B"
SIDE⁽²⁾ “B”
R/W"B"
tSPS
MATCH
SEM"B"
3603 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
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