IDT70V27S_12 Datasheet, PDF (1/21 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
Features:
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed access}
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/35ns (max.)
◆ _{Low-power operation}
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660µW (typ.)
◆ _{Separate upper-byte and lower-byte control for bus}
matching capability
◆ _{Dual chip enables allow for depth expansion without}
external logic
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
◆ _{IDT70V27 easily expands data bus width to 32 bits or more}
using the Master/Slave select when cascading more than
one device
◆ _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
◆ _{Busy and Interrupt Flags}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{LVTTL-compatible, single 3.3V (±0.3V) power supply}
◆ _{Available in 100-pin Thin Quad Flatpack (TQFP), and 144-}
pin Fine Pitch BGA (fpBGA)
◆ _{Industrial temperature range (-40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O8-15L
I/O0-7L
BUSYL ^(1,2)
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
70V27
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
NOTES:
INT
(2)
L
M/S ⁽²⁾
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2012 Integrated Device Technology, Inc.
6.011
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
,
BUSYR^(1,2)
A14R
A0R
SEMR
INTR⁽²⁾
3603 drw 01
SEPTEMBER 2012
DSC 3603/12