IDT5T93GL06 Datasheet, PDF (12/15 Pages) Integrated Device Technology – 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II

IDT5T93GL06
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
A1 - A1
+VDIF
VDIF=0
-VDIF
A2 - A2
+VDIF
VDIF=0
-VDIF
VIH
G
VTHI
VIL
VIH
PD
VTHI
VIL
Qn - Qn
+VDIF
VDIF=0
-VDIF
Power Down Timing
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after
asserting PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn - Qn goes to VDIF = 0.
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