IDT5T93GL06 Datasheet, PDF (11/15 Pages) Integrated Device Technology – 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II

IDT5T93GL06
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
A1 - A1
A2 - A2
SEL
FSEL
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
Qn - Qn
+VDIF
VDIF=0
-VDIF
FSEL Operation to Protect Against When Opposite Clock Dies
NOTES:
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL
pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with
the input clock selected by the SEL pin.
A1 - A1
A2 - A2
FSEL
SEL
Qn - Qn
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF=0
-VDIF
Selection of Input While Protecting Against When Opposite Clock Dies
NOTES:
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL
pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with
the input clock selected by the SEL pin.
11