IDT72103 Datasheet, PDF (11/31 Pages) Integrated Device Technology – CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9

IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
R
COMMERCIAL TEMPERATURE RANGES
(1)
EF
t REF(2)
(3)
W
t WEF
NOTES:
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1. Data is valid on this edge.
2. The Empty Flag is asserted by R in the Parallel-Out mode and is specified by tREF. The EF flag is deasserted by the rising edge of W.
3. First rising edge of Write after EF is set.
Figure 6. Empty Flag Timings in Parallel Out Mode
W
FF
tRFF ⁽¹⁾
R
tWFF
NOTE:
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1. For the assertion time, tWFF is used when data is written in the Parallel mode. The FF is de-asserted by the rising edge of R.
Figure 7. Full Flag Timings in Parallel-In Mode
t WF
W
R
Almost
AEF Empty
Figure 8. Almost-Empty Flag Region
W
t RF
R
Almost
Empty
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AEF
t WF
t RF
Almost
Full
Figure 9. Almost-Full Flag Region
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5.37
11